Jensen Huang met C.C. Wei in Taipei to confirm Vera Rubin in full production at TSMC and to push the conversation forward to Feynman. Gurufocus's summary of the Computex week activity captures the scale: Vera Rubin is now framed by Huang as the largest product launch in Taiwanese history, Feynman is positioned to be the first customer on TSMC's A16 1.6 nm process in the second half of 2026, and Nvidia has reserved the majority of TSMC's latest-generation CoWoS-L advanced packaging.
Wafer count gets the headlines. CoWoS allocation is what determines how many finished Blackwell, Rubin, and Feynman packages actually land in a rack. A package shortage means accelerator shortage, which means the cooling deployments scheduled against that accelerator slip with it. Nvidia locking the majority of CoWoS-L is an explicit signal that the bottleneck has moved downstream of the wafer, and any cooling vendor sizing a 2027 pipeline against wafer commentary is reading the wrong line in the report.
The same logic applied to the previous generation. Hyperscale customers who slotted liquid cooling capex against an aspirational Blackwell delivery schedule discovered that CoWoS was the gating item. This time around, the schedule risk is concentrated at TSMC's packaging line, and that line has one dominant claimant.
A 1.6 nm process delivers more transistors at a lower voltage per switch, which is what makes Feynman possible. It does not deliver lower total package power. Nvidia has consistently used each node shrink to push compute density rather than energy budget, which is the pattern documented across the wattage roadmap. Feynman at A16 is a near-certain step up in rack-level heat flux relative to Vera Rubin. The cooling design point for an A16-generation Nvidia accelerator is going to start where current Rubin practice tops out, which means CDU sizing, coolant flow budget, and rejection capacity all need to be specified against that ceiling now.
Three numbers matter for the next eighteen months and they are not published on Nvidia's keynote slides. CoWoS-L throughput at the TSMC line in Taiwan and Arizona. The package power envelope Nvidia communicates privately to OEM partners for the Feynman board. And the OEM partner-board reference design for A16-class accelerators, which sets the inlet temperature spec every cold plate vendor has to design against. A vendor that does not have access to those three numbers is sizing 2027 by analogy with 2025. That gap is where the investor re-rating of cooling vendors now lives.